Conventionally, in order to carry out mounting with a narrow pitch, wiring boards are widely used, which wiring boards have pads disposed thereon in so-called plurality of rows.
Along with the demand for further reduction of size and weight of electronic apparatuses that use the wiring board, electronic components mounted in such electronic apparatuses are becoming more compact. This demand has also caused a demand for achieving a further narrow pitch in a wiring board which is a substrate on which the electronic components are mounted.
(Patent Literature 1)
Various techniques have been proposed to meet such demands. For example, Patent Literature 1 discloses a technique of a wiring board which mounts pads that are disposed in a plurality of rows. The wiring board provides the pads in a layer different from metal wires that pass between the pads disposed adjacent to each other, and further the pads are provided to have a double-layered structure. The following description explains this technique with reference to FIGS. 23 and 24. FIG. 23 is a view illustrating a configuration of a wiring board disclosed in Patent Literature 1, and FIG. 24 is a cross-sectional view taken along line X-X in FIG. 23. The “first row” and “second row” in FIG. 23 are names provided to respective rows in which pads 105 are disposed.
As illustrated in FIG. 23, a wiring board 100 disclosed in Patent Literature 1 has metal wires 101 disposed between adjacent pads 105 in the second row among the pads 105 disposed in the plurality of rows. Each of the metal wires 101 is connected to a respective one of the pads 105 in the first row. The metal wires 101 are provided in a layer different from the pads 105 in the second row, as illustrated in FIG. 24. Namely, the pads 105 are provided in an upper layer of the metal wires 101 as a layer different from the metal wire 101, in such a manner that an interlayer insulating layer 102 is provided between the pads 105 and the metal wires 101.
Moreover, each of the pads 105 in the first row and the second row are connected to a respective one of the metal wires 101 provided in the layer different from that of the pads 105, via a through-hole 103 (see FIG. 23). Furthermore, a pad 109 having an area larger than that of the pad 105 is provided in an upper layer of each of the pads 105, via an interlayer insulating layer 106. The pads 105 and pads 109 are connected via a pad through-hole 107 (see FIG. 23). That is to say, the metal wires 101, the pads 105, and the pads 109 are provided in different layers; i.e., the metal wires 101 are provided in a first layer, the pads 105 are provided in a second layer, and the pads 109 are provided in a third layer.
As described above, the wiring board 100 disclosed in Patent Literature 1 has the metal wires 101 that are disposed between the pads 105 in the second row be provided in a different layer from the pads 105 and pads 109 (the interlayer insulating layer 102 is provided in an upper layer of the metal wires 101). This makes it possible to reduce spaces between adjacent pads 109 to a certain degree.
(Patent Literature 2)
The following description explains an example of a case where the wiring board, which wiring board is a substrate on which an electronic component is mounted, is used as a substrate for use in a display device, with reference to Patent Literature 2.
Patent Literature 2 discloses a configuration in which pads disposed in the plurality of rows are formed on a liquid crystal panel. The following description is provided with reference to FIGS. 25 to 27. FIG. 25 is a view illustrating a configuration of a liquid crystal panel disclosed in Patent Literature 2, FIG. 26 is a view illustrating a configuration of a bottom side of a driving IC (Integrated Circuit) illustrated in FIG. 25, and FIG. 27 is a view illustrating a liquid crystal panel on which the driving IC illustrated in FIG. 26 is mounted.
As illustrated in FIG. 25, the liquid crystal panel 300 disclosed in Patent Literature 2 has a driving IC 400 directly mounted on the liquid crystal panel 300 (COG (Chip On Glass) mounting). On a bottom side of the driving IC 400 that is COG mounted on the liquid crystal panel 300, bumps 410 are disposed in a plurality of rows, as illustrated in FIG. 26. Further, in a region of the liquid crystal panel 300 on which the driving IC 400 is mounted, electrode pads 320 that correspond to the bumps 410 disposed on the bottom side of the driving IC 400 are provided, as illustrated in FIG. 27. The electrode pads 320 are connected to input lines 310, respectively, which input lines 310 are wires connecting to the pads.